1. Field of the Invention
The present invention generally relates to soft error correction methods, memory control apparatuses and memory systems, and more particularly to a soft error correction method for correcting a soft error within a memory, a memory control apparatus suited for such a soft error correction method, and a memory system that employs such a soft error correction method.
2. Description of the Related Art
FIG. 1 is a system block diagram showing an example of a conventional memory system. A memory system 10 shown in FIG. 1 has a structure for accessing byte-sliced data, that is, data that have been sliced in units of bytes. The memory system 10 includes a plurality of memories (MEMs) 1-1 through 1-n, a plurality of memory access controllers (MACs) 2-1 through 2-n, a system controller (SC) 3, and a plurality of MPUs 5-1 through 5-m. In FIG. 1, a data bus is indicated by a white arrow, an address bus is indicated by a bold solid line arrow, and a status bus is indicated by a solid line arrow.
The memory access controllers 2-1 through 2-n are constructed to access the memories 1-1 through 1-n in units of bytes of the byte-sliced data, at synchronized access cycles. In other words, all of the memory access controllers 2-1 through 2-n constantly and simultaneously carry out the memory accesses with respect to all of the memories 1-1 through 1-n at the same timing, so that no synchronization error is generated in the accesses to the memories 1-1 through 1-n.
On the other hand, in the memories 1-1 through 1-n that are made up of memory devices such as DRAMs and SRAMs, a soft error is generated at a predetermined probability. Hence, in a case where reliability is required of the memory system 10, the data within the memories 1-1 through 1-n are corrected using a data protection mechanism such as the ECC.
For example, if a correctable soft error is generated in one memory 1-1 and the system controller 3 detects this soft error, generally, the hardware of the system controller 3 carries out an error correction operation by itself. In this case, the following series of operations are required.
FIGS. 2 and 3 are diagrams for explaining the error correction operation in such a case. FIG. 2 is a system block diagram functionally showing an important part of the memory system 10, and FIG. 3 is a time chart for explaining the error correction operation. In FIG. 2, a dotted line arrow indicates a command flow, a bold dotted line arrow indicates an address flow, a solid line arrow indicates a status flow, and a bold solid line arrow indicates a data flow. In addition, numerals in brackets in FIG. 2 indicate the number of bits.
As shown FIG. 2, each of the memory access controllers 2-1 through 2-n includes registers 521, 522, 525 and 526 in addition to a controller (not shown). The system controller 3 includes selectors 531 and 532, registers 533 and 534, an AND circuit 535, an error detecting part 536, a selector 537, an error correcting part 538 and a register 539, in addition to a controller (not shown).
First, as shown in FIGS. 2 and 3, when a read command from the MPU 5-1 is input to the system controller 3 together with an address, the system controller 3 inputs the read command (Read cmd) and the address (Address) to the memory access controller 2-1 via the selectors 531 and 532. The read command (Command) and the address (Address) are temporarily held in the registers 521 and 522 of the memory access controller 2-1, and input to the memory 1-1 at a memory prescribed timing. The data (Data) read from the memory 1-1 (MEM Read) and including an ECC are input to the memory access controller 2-1 and temporarily held in the register 525 within the memory access controller 2-1, and input to the system controller 3 at a memory prescribed timing. If no error (Error) exists in the read data (Read Data) as a result of the error detection (Read Data Check) using the ECC in the error detecting part 536 of the system controller 3, the read data (Correct Data) is input to the MPU 5-1.
On the other hand, if an error exists in the read data as a result of the error detection using the ECC in the system controller 3, but the read data (Error Data) is correctable by the ECC (Error Correct), a read command (Scrub cmd) for correcting the error with respect to the address (Error Address) where the error was detected is input to the memory access controller 2-1, so as to read the error data (Error Data) from the memory 1-1. Since the error in the read data is correctable using the ECC in the error correcting part 538 of the system controller 3, the read data is input to the error correcting part 538 via the register 539 and the selector 537 and corrected, and the corrected data (corrected read data) is input to the memory access controller 2-1 together with a write command for correcting the error. The memory access controller 2-1 temporarily holds the corrected data in the register 526, and rewrites the corrected data to the address where the above described error was detected, at a prescribed timing. Hence, the correctable soft error within the memory 1-1 is corrected.
In the case of a normal data write (MEM Write), the write data from the MPU 5-1 is input to the memory access controller 2-1 via the system controller 3.
As described above, the memory system 10 is constructed so that all of the memory access controllers 2-1 through 2-n constantly and simultaneously carry out the memory accesses with respect to all of the memories 1-1 through 1-n at the same timing. For this reason, a soft error correction operation similar to the soft error correction operation with respect to the memory 1-1 via the memory access controller 2-1 is simultaneously carried out with respect to the memories 1-2 through 1-n via the other memory access controllers 2-2 through 2-n, regardless of whether or not the soft error exists in the memories 2-2 through 2-n.
A system for remedying a memory error has been proposed in a Japanese Laid-Open Patent Application No. 59-217298, for example.
However, in the conventional memory system, the error detection and the error correction are carried out in the system controller. As a result, there were problems in that the structure of the system controller becomes complex, and the load on the system controller is large. In addition, there was a problem in that the application cannot be made with respect to a memory system in which the system controller and a crossbar switch are separate.